A Day in the Life of a Data Cache Miss

The activity within a processor following a cache miss is studied via a series of simulation experiments. This is a preliminary step toward developing ways of mitigating data cache miss penalties, especially for long misses. With a modest-sized reorder buffer (ROB) of 64 entries, structural blockages due to a full ROB are the major cause of the cache miss penalty. For the SpecINT2000 benchmarks, about 90% of long cache misses result in a blocked ROB. After structural constraints are removed, data dependences are found not to be a major cause of performance loss. In fact, instruction issuing can proceed at full speed for at least one thousand cycles (the length we sampled) beyond a data cache miss. In some cases we found control dependences do pose a problem, however. That is, there are many mispredicted branches that depend on data from a cache miss. With an 8K gshare predictor, 30% or more of data cache misses feed into a mispredicted branch in 7 of 12 benchmarks. Finally, we discuss implications for future processor designs. This includes lengthening ROBs (and enlarging physical rename locations), coupled with a more modest enlarging of instruction issue windows.